Check out the all new Au V2!

If you're looking for an original Au available now, head over to SparkFun.

Development Stage

• Design (schematic creation and PCB layout)
• Prototype Build (part sourcing and ordering of initial prototype)
• Prototype Evaluation (prototype is in hand, design is being tested)
• Part Sourcing
• Initial Production Run

Features

• XC7A35T-2FTG256C FPGA (speed grade upgrade over Au V1)
• 104 IO pins broken out across two headers
  • 22 are dual voltage (2.5V or 3.3V) of which 20 are LVDS_25 capable outputs
  • 44 pins are routed as 100 ohm differential pairs (includes 20 dual voltage pins)
  • Remaining IO routed as 50 ohm single ended (~90 ohm when used as diff pairs)
  • 2 1.35V pins on bank B
  • 8 pairs can be used as inputs to the XADC (0-1V input range)
  • Remaining IO is at 3.3V
  • All pairs can be used as LVDS_25 inputs except three pairs on bank B
• Control Header
  • 8 IO pins also connected to on-board LEDs
  • 1 IO pin also connected to on-board reset button
  • JTAG
  • Analog voltages and dedicated XADC input (0-1V range)
  • Raw power input/3.3V regulated output
• QWIIC connector (shares pins on bank B)
• 100MHz oscillator
• 8 general purpose LEDs
• 1 button (typically used as reset)
• 256MB DDR3L @ 800Mb/s (400MHz)
• 32MBit Configuration FLASH
• FT2232HQ USB -> JTAG and USB -> UART (12Mbaud max)
• 5-12V input voltage on-board power supply
  
  • 3.3V @ 4A (IO)
  • 2.5V @ 500mA (dual voltage pins, derived from 3.3V)
  • 1V @ 4A (VCCINT)
  • 1.8V @ 1.2A (VCCAUX)
  • 1.35V @1.2A (DDR3L)
    
  • 1.8V @ 200mA (analog)

Documents

• Schematic
• Pinout and Trace Lengths
• Drawing (Connector Positions)
• 3D Model (STEP)