Expected to ship in Q2.

Check out the all new Alchitry Pt!

The Artix 7 FPGA requires a free license for Vivado. Click here for instructions on installing it.

This board is in the early design stage and the render is just for illustration purposes.

Development Stage

• Design (schematic creation and PCB layout)
• Prototype Build (part sourcing and ordering of initial prototype)
• Prototype Evaluation (prototype is in hand, design is being tested)
• Part Sourcing
• Initial Production Run

Features

• XC7A100T-2FGG84I FPGA
• Connectors on both sides of the board allow two independant stacks (IO isn't shared)
• 206 IO pins
  • All IO pairs are LVDS_25 capable inputs or TMDS_33 capable IO 
  • 112 on the top
    • 32 triple voltage (3.3V, 2.5V, or 1.8V) pins (16 pairs) capable of LVDS_25 IO
    • 76 routed as 100 ohm differential pairs
    • Remaining IO routed as 50 ohm single ended
    • 8 are on the control header
  • 92 on the bottom
    • 24 routed as 100 ohm differential pairs
    • Remaining IO routed as 50 ohm single ended
    • 8 are on the control header
  • 2 on QWIIC connector
• 20 GTP pins broken out on the bottom
  • 2 clock input pairs
  • 4 Tx pairs
  • 4 Rx pairs
  • 6.25 Gb/s bandwidth per pair
    
• 100MHz oscillator
• 8 general purpose LEDs
• 1 button (typically used as reset)
• 256MB DDR3L @ 800Mb/s (400MHz)
• 32MBit Configuration FLASH
• FT2232HQ USB -> JTAG and USB -> UART (12Mbaud max) or FIFO (~20MB/s)
• 5-12V input voltage on-board power supply
  
  • 3.3V @ 4A (IO)
  • 2.5V @ 500mA (triple voltage pins, derived from 3.3V)
  • 1V @ 4A (VCCINT)
  • 1.8V @ 1.2A (VCCAUX, triple voltage pins)
  • 1.35V @1.2A (DDR3L)
    
  • 1.8V @ 200mA (analog)
  • 1V @ 1.5A (MGTAVCC, derived from 3.3V)
  • 1.2V @1.5A (MGTAVTT, derived from 3.3V)