Expected around the end of July.

Check out the all new Alchitry Pt!

The Artix 7 FPGA requires a free license for Vivado. Click here for instructions on installing it.

The Pt was designed so that no components on the bottom are taller than 1.5mm allowing a for use of the high speed 1.5mm stack-height DF40 connectors. This requires that the mating board is clear of components under the Pt.

Due to physical conflicts, the bottom side of the Pt cannot be directly connected to the Ft, Ft+, or Hd. A Br, Fn, or Sp must be between the boards to prevent the connectors from contacting capacitors on the bottom the Pt.

Features

• XC7A100T-2FGG84I FPGA
• Connectors on both sides of the board allow two independent stacks (IO isn't shared)
• 206 IO pins
  • All IO pairs are LVDS_25 capable inputs or TMDS_33 capable IO 
  • 112 on the top
    • Routed as differential pairs
    • 32 triple voltage (3.3V, 2.5V, or 1.8V) pins (16 pairs) capable of LVDS_25 IO
    • 8 are on the control header
  • 92 on the bottom
    • Routed as differential pairs
    • 8 are on the control header
  • 2 on QWIIC connector
• 20 GTP pins broken out on the bottom
  • 2 clock input pairs
  • 4 Tx pairs
  • 4 Rx pairs
  • 6.25 Gb/s bandwidth per pair
    
• 100MHz oscillator
• 8 general purpose LEDs
• 1 button (typically used as reset)
• 256MB DDR3L @ 800Mb/s (400MHz)
• 32MBit Configuration FLASH
• FT2232HQ USB -> JTAG and USB -> UART (12Mbaud max) or FIFO (~8MB/s)
• 5-12V input voltage on-board power supply
  
  • 3.3V @ 4A (IO)
  • 2.5V @ 500mA (triple voltage pins, derived from 3.3V)
  • 1V @ 4A (VCCINT)
  • 1.8V @ 1.2A (VCCAUX, triple voltage pins)
  • 1.35V @1.2A (DDR3L)
    
  • 1.8V @ 200mA (analog)
  • 1V @ 1.5A (MGTAVCC, derived from 3.3V)
  • 1.2V @1.5A (MGTAVTT, derived from 3.3V)

Documents

• Schematic
• 3D Model (STEP)
• DC and AC Switching Characteristics (DS181)
• SelectIO Resources (UG471)
• Clocking Resources (UG472)
• All Xilinx Artix 7 Docs